`timescale 1ns/1ps
module test();

	parameter NOP = 4'b0000;
	parameter ADD = 4'b0001;
	parameter SUB = 4'b0010;
	parameter AND = 4'b0011;
	parameter NOT = 4'b0100;
	parameter RD  = 4'b0101;
	parameter WR  = 4'b0110;
	parameter BR  = 4'b0111;
	parameter BRZ = 4'b0111;
	
	parameter SEL_R0 = 2'd0;
	parameter SEL_R1 = 2'd1;
	parameter SEL_R2 = 2'd2;
	parameter SEL_R3 = 2'd3;

	
	
	logic clk, rst_n;
	
	initial begin
	    clk = 1'b0;
		forever #5ns clk = ~clk;
	end
	
	initial begin
		$timeformat(-9, 3," ns ", 5);
	    rst_n = 1'bx;
		#18ns rst_n = 1'b0;
		#18ns rst_n = 1'b1;
	end
	
	initial begin
		foreach(U_RISC_SPM.U_MEM.mem[i])begin
			U_RISC_SPM.U_MEM.mem[i] = '0;
		end
	end
	
	initial begin
		wait(rst_n == 1'b1);
		U_RISC_SPM.U_PROCESSING.U_R0.data_out = 8'h3;
		U_RISC_SPM.U_PROCESSING.U_R1.data_out = 8'h4;
		U_RISC_SPM.U_PROCESSING.U_R2.data_out = 8'h5;
		U_RISC_SPM.U_PROCESSING.U_R3.data_out = 8'h6;
		U_RISC_SPM.U_MEM.mem[0] = {RD, SEL_R1, SEL_R1};
		U_RISC_SPM.U_MEM.mem[1] = 129;
		U_RISC_SPM.U_MEM.mem[2] = {RD, SEL_R2, SEL_R2};
		U_RISC_SPM.U_MEM.mem[3] = 130;
		U_RISC_SPM.U_MEM.mem[4] = {BR, SEL_R2, SEL_R2};
		U_RISC_SPM.U_MEM.mem[5] = 10;
		U_RISC_SPM.U_MEM.mem[129] = 100;
		U_RISC_SPM.U_MEM.mem[130] = 150;
		U_RISC_SPM.U_MEM.mem[10] = 28;
		U_RISC_SPM.U_MEM.mem[28]  = {SUB, SEL_R1, SEL_R2};
	end
	
	RISC_SPM U_RISC_SPM(clk, rst_n);
	
endmodule